`timescale  1ms/100us
module paobiao_test
  reg clk,clr,pause;
  wire [3:0] msh,msl,sh,sl,mh,ml;
  wire cn1,cn2;
  paobiao u1(clk,clr,pause,msh,msl,sh,sl,mh,ml);
   always #5 clk= ~clk;
   initial
   begin
   clk=0;
   clr=1;
   pause=0;
   #10 clr=0;pause=1;
 end
 initial 
  $monitor($time, , ,"clk=%d?clr=%d,msh=%d,msl=%d,sh=%d,sl=%d,mh=%d,ml=%d",clk,clr,msh,)